Exact Minimum-Width Transistor Placement for General CMOS Cells

This chapter shows a minimum-width transistor placement method which is applicable to CMOS cells in presence of non-dual P and N type transistors, whereas the cell layout synthesis methods explained in the previous chapters are only for dual cells. This chapter only targets the minimum-width transistor placement, and does not take the intra-cell routings into consideration. The proposed method are the first exact method which can be applied to CMOS cells with any types of structure, whereas almost all of the conventional exact transistor placement method[19, 22, 24] are applicable only to dual CMOS cells. All of these methods make pairs of complementary P and N type transistors and align them in minimum width. Therefore, all these methods can not be applied to some cells that have non-dual P and N type transistors. Even for the dual circuits, these methods can not always generate the minimum-width layouts, since the width depends on pairing of P and N type transistors. Since non-dual CMOS cells occupy a major part of an industrial standard-cell library, the exact minimum-width transistor placement should be applied even to non-dual CMOS cells. Zhang et a/.[31] proposed the novel transistor pairing algorithm which is applicable to the cells including non-series-parallel networks. This algorithm decides pairs of P and N type transistors for general complex gates, in which there are more than two transistors with a common input signal in their gates, so that the resulting cell width is minimized. This method, however, is not an exact method and generates large placement when a given cell has a transistor which does not have a pair transistor with the common gate input signal. We have proposed a cell layout synthesis method using Boolean Satisfiability (SAT) in Chapter 2. This method can generate an exact minimum-width transistor placement for non-